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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
August 1999
NM24C16U/NM24C17U 16K-Bit Serial EEPROM 2-Wire Bus Interface
General Description
The NM24C16U/17U devices are 16K (16,384) bit serial interface CMOS EEPROMs (Electrically Erasable Programmable ReadOnly Memory). These devices fully conform to the Standard I2CTM 2-wire protocol which uses Clock (SCL) and Data I/O (SDA) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the EEPROM device). In addition, the serial interface allows a minimal pin count packaging designed to simplify PC board layout requirements and offers the designer a variety of low voltage and low power options. NM24C17U incorporates a hardware "Write Protect" feature, by which, the upper half of the memory can be disabled against programming by connecting the WP pin to VCC. This section of memory then effectively becomes a ROM (Read-Only Memory) and can no longer be programmed as long as WP pin is connected to VCC. Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption for a continuously reliable non-volatile solution for all markets.
Functions
I I2CTM compatible interface I 4,096 bits organized as 512 x 8 I Extended 2.7V - 5.5V operating voltage I 100 KHz or 400 KHz operation I Self timed programming cycle (6ms typical) I "Programming complete" indicated by ACK polling I NM24C17U: Memory "Upper Block" Write Protect pin
Features
I The I2CTM interface allows the smallest I/O pincount of any EEPROM interface I 16 byte page write mode to minimize total write time per byte I Typical 200A active current (ICCA) I Typical 1A standby current (ISB) for "L" devices and 0.1A standby current for "LZ" devices I Endurance: Up to 1,000,000 data changes I Data retention greater than 40 years
Block Diagram
VCC VSS WP H.V. GENERATION TIMING &CONTROL START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR E2PROM ARRAY
SDA
SCL
XDEC
WORD ADDRESS COUNTER
R/W
YDEC
CK DIN DATA REGISTER DOUT
DS800010-1
I2CTM is a registered trademark of Philips Electronics N.V.
(c) 1999 Fairchild Semiconductor Corporation NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Connection Diagrams
Dual-In-Line Package (N), 8-Pin SO Package (M8)
NC NC NC VSS 1 2 3 4 8 7 VCC NC SCL SDA
DS800010-2
8-Pin TSSOP Package (MT8) Rotated Die (24C16UT)
NC VCC NC NC 1 2 3 4 8 7 SCL SDA VSS NC
DS800010-3
NM24C16U
6 5
NM24C16UT
6 5
Top View See Package Number N08E, M08A and MTC08
Pin Names
VSS SDA SCL NC VCC Ground Serial Data I/O Serial Clock Input No Connection Power Supply
Dual-In-Line Package (N), 8-Pin SO Package (M8)
NC NC NC VSS 1 2 3 4 8 7 VCC WP SCL SDA
DS800010-4
8-Pin TSSOP Package (MT8) Rotated Die (24C17UT)
WP VCC NC NC 1 2 3 4 8 7 SCL SDA VSS NC
DS800010-5
NM24C17U
6 5
NM24C17UT
6 5
Top View See Package Number N08E, M08A and MTC08
Pin Names
VSS SDA SCL WP VCC NC Ground Serial Data I/O Serial Clock input Write Protect Power Supply No Connection
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Ordering Information NM 24 C XX U F T LZ E XX
Package
Letter
N M8 MT8 None V E Blank L LZ
Description
8-pin DIP 8-pin SOIC 8-pin TSSOP 0 to 70C -40 to +125C -40 to +85C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V and <1A Standby Current Normal Pin Out Rotated Die Pin Out 100KHz 400KHz CS100UL Process 16K 16K with Write Protect CMOS Technology Total Array Write Protect IIC Fairchild Non-Volatile Memory
Temp. Range
Voltage Operating Range
Blank T SCL Clock Frequency Blank F Ultralite Density 16 17 C W Interface 24 NM
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Product Specifications Absolute Maximum Ratings
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating -65C to +150C 6.5V to -0.3V +300C 2000V min.
Operating Conditions
Ambient Operating Temperature NM24C16U/17U NM24C16UE/17UE NM24C16UV/17UV Positive Power Supply NM24C16U/17U NM24C16UL/17UL NM24C16ULZ/17ULZ 0C to +70C -40C to +85C -40C to +125C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Min
ICCA ISB ILI ILO VIL VIH VOL Active Power Supply Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage IOL = 3 mA fSCL = 400 KHz fSCL = 100 KHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC -0.3 VCC x 0.7
Limits Typ (Note 1)
0.2 10 0.1 0.1
Units Max
1.0 50 1 1 VCC x 0.3 VCC + 0.5 0.4 mA A A A V V V
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Min
ICCA ISB Active Power Supply Current fSCL = 400 KHz fSCL = 100 KHz Standby Current VIN = GND or VCC VCC = 2.7V - 4.5V VCC = 2.7V - 4.5V VCC = 4.5V - 5.5V
Limits Typ (Note 1)
0.2 1 0.1 10 0.1 0.1
Units Max
1.0 10 1 50 1 1 VCC x 0.3 VCC + 0.5 0.4 mA A A A A A V V V
ILI ILO VIL VIH VOL
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage
VIN = GND to VCC VOUT = GND to VCC -0.3 VCC x 0.7 IOL = 3 mA
Capacitance TA = +25C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
CI/O CIN
Test
Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL)
Conditions
VI/O = 0V VIN = 0V
Max
8 6
Units
pF pF
Note 1: Typical values are TA = 25C and nominal supply voltage (5V). Note 2: This parameter is periodically sampled and not 100% tested.
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
AC Conditions of Test
Input Pulse Levels Input Rise and Fall Times Input & Output Timing Levels Output Load VCC x 0.1 to VCC x 0.9 10 ns VCC x 0.5 1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
fSCL TI
Parameter
SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN Pulse width) SCL Low to SDA Data Out Valid Time the Bus Must Be Free before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time - NM24C16U/17U - NM24C16U/17UL, NM24C16U/17ULZ
100 KHz Min Max
100 100 0.3 4.7 4.0 4.7 4.0 4.7 0 250 1 300 4.7 300 10 15 3.5
400 KHz Min Max
400 50 0.1 1.3 0.6 1.5 0.6 0.6 0 100 0.3 300 0.6 50 10 15 0.9
Units
KHz ns s s s s s s s ns s ns s ns ms
tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tWR (Note 3)
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the NM24C16U/17U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Bus Timing
tF tHIGH tLOW SCL tLOW tR
SDA
SDA
OUT
System Layout
Typical System Configuration
;;
tSU:STA tHD:STA IN
tHD:DAT
tSU:DAT
tSU:STO
tBUF tDH
tAA
DS800010-8
VCC
VCC
SDA SCL Master Transmitter/ Receiver
Note:
Slave Receiver
Slave Transmitter/ Receiver
Master Transmitter
Master Transmitter/ Receiver
DS800010-20
Due to open drain configuration of SDA, a bus-level pull-up resistor is called for, (typical value = 4.7k)
Example of 16K of Memory on 2-Wire Bus Device A0
NM24C16U/17U No Connect
Address Pins A1
No Connect
Memory Size A2
No Connect 16,384 Bits
# of Page Blocks
8
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Device Operation
Background Information (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock) and SDA (Data I/O) lines. All communication must be started with a valid START condition, concluded with a STOP condition and acknowledged by the Receiver with an ACKNOWLEDGE condition. As shown below, the EEPROMs on the IIC bus may be configured in any manner required, the total memory addressed can not exceed 16K (16,384 bits). EEPROM memory address programming is controlled by 2 methods: * All unused pins must be grounded (tied to VSS). * Software addressing the required PAGE BLOCK within the device memory array (as sent in the Slave Address string). For devices with densities greater than 16K, a different protocol, the Extended IIC protocol, is used. Refer to NM24C32U datasheet (for example) for additional details. Addressing an EEPROM memory location involves sending a command string with the following information: [DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK ADDRESS]-[BYTE ADDRESS]
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
WP Write Protection (NM24C17U Only)
If tied to VCC, PROGRAM operations onto the upper half of the memory will not be executed. READ operations are possible. If tied to VSS, normal operation is enabled, READ/WRITE over the entire memory is possible. This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming. When write is disabled, slave address and word address will be acknowledged but data will not be acknowledged.
Device Operation
The NM24C16U/17U supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the NM24C16U/17U will be considered a slave in all applications.
DEFINITIONS
WORD PAGE 8 bits (byte) of data 16 sequential addresses (one byte each) that may be programmed during a 'Page Write' programming cycle 2048 (2K) bits organized into 16 pages of addressable memory. (8 bits) x (16 pages) = 2048 bits Any IIC device CONTROLLING the transfer of data (such as a microprocessor) Device being controlled (EEPROMs are always considered Slaves) Device currently SENDING data on the bus (may be either a Master or Slave). Device currently RECEIVING data on the bus (Master or Slave)
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figure 2 and Figure 3 on next page.
PAGE BLOCK
MASTER
Start Condition
All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The NM24C16U/17U continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
SLAVE
TRANSMITTER
Stop Condition
All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the NM24C16U/17U to place the device in the standby power mode.
RECEIVER
Write Cycle Timing
Acknowledge
Acknowledge is a hardware convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line to LOW to acknowledge that it received the eight bits of data. Refer to Figure 4.
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Write Cycle Timing (Figure 1)
SCL
SDA
8th BIT WORD n
ACK tWR STOP CONDITION START CONDITION
DS800010-10
Note:
The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
Data Validity (Figure 2)
SCL
SDA
DATA STABLE DATA CHANGE
DS800010-11
Start and Stop Definition (Figure 3)
SCL
SDA START CONDITION STOP CONDITION
DS800010-12
Acknowledge Response from Receiver (Figure 4)
SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START
ACKNOWLEDGE
DS800010-13
1
8
9
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Write Cycle Timing (Continued)
The NM24C16U/17U device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the NM24C16U/17U will respond with an acknowledge after the receipt of each subsequent eight bit byte. In the read mode the NM24C16U/17U slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode.
Refer to the following table for Slave Addresses string details:
Device
A0 A1 A2 Page Blocks
P P 8
Page Block Addresses
000 001 010 011 ... 111
NM24C16U/17U P
P: Refers to an internal PAGE BLOCK memory segment.
All IIC EEPROMs use an internal protocol that defines a PAGE BLOCK size of 2K bits (for Word addressess 0000 through 1111). Therefore, address bits A0, A1, or A2 (if designated 'P') are used to access a PAGE BLOCK in conjunction with the Word address used to access any individual data byte (Word). The last bit of the slave address defines whether a write or read condition is requested by the master. A '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. A simple review: After the NM24C16U/17U recognizes the start condition, the devices interfaced to the IIC bus wait for a slave address to be transmitted over the SDA line. If the transmitted slave address matches an address of one of the devices, the designated slave pulls the line LOW with an acknowledge signal and awaits further transmissions.
Device Addressing
Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are those of the device type identifier (see Figure 5). This is fixed as 1010 for all EEPROM devices.
Slave Addresses (Figure 5)
Device Type Identifier
1
0
1
0
A2
A1
A0
R/W
(LSB)
NM24C16U/17U Page Block Address
DS800010-14
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Write Operations
BYTE WRITE
For a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. Upon receipt of the byte address the NM24C16U/17U responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the NM24C16U/17U begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the NM24C16U/17U inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 6 for the address, acknowledge and data transfer sequence.
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host's write operation the NM24C16U/17U initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the NM24C16U/17U is still busy with the write operation no ACK will be returned. If the NM24C16U/17U has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation.
Write Protection (NM24C17U Only)
Programming of the upper half of the memory will not take place if the WP pin of the NM24C17U is connected to VCC. The NM24C17U will accept slave and byte addresses; but if the memory accessed is write protected by the WP pin, the NM24C17U will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted.
PAGE WRITE
The NM24C16U/17U is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. After the receipt of each byte, the NM24C16U/17U will respond with an acknowledge. After the receipt of each byte, the internal address counter increments to the next address and the next SDA data is accepted. If the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 7 for the address, acknowledge, and data transfer sequence.
Byte Write (Figure 6)
S T A R T S T O P
Bus Activity: Master SDA Line Bus Activity: NM24C16U/17U
SLAVE ADDRESS
WORD ADDRESS
DATA
A C K
A C K
A C K
DS800010-15
Page Write (Figure 7)
S T A R T S T O P
Bus Activity: Master SDA Line Bus Activity: NM24C16U/17U
SLAVE ADDRESS
WORD ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
A C K
A C K
A C K
A C K
A C K
DS800010-16
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Read Operations
Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read, and sequential read.
start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the NM24C16U/17U and then by the eight bit data. The master will not acknowledge the transfer but does generate the stop condition, and therefore the NM24C16U/17U discontinues transmission. Refer to Figure 9 for the address, acknowledge and data transfer sequence.
Current Address Read
Internally the NM24C16U/17U contains an address counter that maintains the address of the last byte accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to one, the NM24C16U/17U issues an acknowledge and transmits the eight bit byte. The master will not acknowledge the transfer but does generate a stop condition, and therefore the NM24C16U/ 17U discontinues transmission. Refer to Figure 8 for the sequence of address, acknowledge and data transfer.
Sequential Read
Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The NM24C16U/17U continues to output data for each acknowledge received. The read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter "rolls over" and the NM24C16U/17U continues to output data for each acknowledge received. Refer to Figure 10 for the address, acknowledge, and data transfer sequence.
Random Read
Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, slave address and then the byte address it is to read. After the byte address acknowledge, the master immediately reissues the
Current Address Read (Figure 8)
Bus Activity: Master SDA Line Bus Activity: NM24C16U/17U A C K NO A C K
DS800010-17
S T A R T
SLAVE ADDRESS
S T O P
DATA
Random Read (Figure 9)
Bus Activity: Master SDA Line Bus Activity: NM24C16U/17U A C K A C K A C K DATA n NO A C K
DS800010-18
S T A R T
SLAVE ADDRESS
WORD ADDRESS
S T A R T
SLAVE ADDRESS
S T O P
Sequential Read (Figure 10)
Bus Activity: Master SDA Line Bus Activity: NM24C16U/17U A C K
DATA n +1 DATA n +1 DATA n + 2 DATA n + x Slave Address
A C K
A C K
A C K
S T O P
NO A C K
DS800010-19
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197 (4.800 - 5.004)
8765
0.228 - 0.244 (5.791 - 6.198)
1234
Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 8 Max, Typ. All leads 0.04 (0.102) All lead tips
0.010 - 0.020 x 45 (0.254 - 0.508)
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254) Seating Plane
0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads
0.016 - 0.050 (0.406 - 1.270) Typ. All Leads
0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508)
8-Pin Molded Small Outline Package (M8) Package Number M08A
0.114 - 0.122 (2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ (0.65) Typ
0.246 - 0.256 (6.25 - 6.5)
0.123 - 0.128 (3.13 - 3.30)
1
4
Pin #1 IDENT
Land pattern recommendation
0.0433 Max (1.1) 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) Typ.
See detail A
0.0035 - 0.0079
0.0075 - 0.0098 (0.19 - 0.30)
0-8
Gage plane
DETAIL A Typ. Scale: 40X
0.020 - 0.028 (0.50 - 0.70) Seating plane
0.0075 - 0.0098 (0.19 - 0.25)
Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded Thin Shrink Small Outline Package Package Number MTC08
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NM24C16U/17U Rev. B.1
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NM24C16U/NM24C17U - 16K-Bit Serial EEPROM 2-Wire Bus Interface
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 0.092 DIA (2.337) Pin #1 IDENT Option 1
0.032 0.005
8
7
8
+
7
6
5
0.250 - 0.005 (6.35 0.127)
(0.813 0.127) RAD Pin #1 IDENT
1 1 2 3 4
0.039 (0.991) 0.130 0.005 (3.302 0.127) Option 2 0.145 - 0.200 (3.683 - 5.080) 0.040 Typ. (1.016)
0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128)
0.030 MAX (0.762) 20 1
95 5 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM
0.065 (1.651)
0.125 - 0.140 (3.175 - 3.556) 90 4 Typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.060 (1.524)
0.020 (0.508) Min
0.045 0.015 (1.143 0.381) 0.050 (1.270)
Molded Dual-In-Line Package (N) Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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NM24C16U/17U Rev. B.1
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